Programming Homework Help

In this question you are to implement the following truth table (where “–“ represents a
don’t care value) using the requested commands/styles in Verilog. Simulate each case using
your testbench and then synthesize each version and submit the screen capture of the RTL
view. (To see your design RTL view, go to Schematic in RTL ANALYSYS). You can
use a Case statement to implement this logic. Test the results and show the waveform for
each input combination and output, and explain.

In this question, you are asked to design a synthesizable ALU in Verilog. This ALU gets
two 9-bit signed inputs (A, B) in 2’s complement format, and a 4-bit select input (S) based
on which decides about the operation that should be executed. The output is Q, and you
determine the number of bits for Q in order to have a correct answer. What follows shows
these operations:

Reconsider question 2 with the assumption that the output is a registered output, i.e., Q is
loaded by the rising edge of the clock signal when reset is not active (RESET=0). Build
the following:
A) Consider a synchronous resetting mechanism (RESET only acts in the rising edge of
the CLK signal). Implement the circuit using a sequential case statement.
B) Consider an asynchronous resetting mechanism (RESET triggers a reset immediately,
not only on the clock signal). Implement the circuit using a sequential case statement.
Note: The only difference betw